Shri Mata Vaishno Devi University
A State University recognized under Section 2 (f) & 12 (B) of UGC Act of 1956
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10052018 Emerging Issues in VLSI Design

A TEQIP-III sponsored One-Week Faculty Development Program (FDP) on “Emerging Issues in VLSI Design” from 7th-11th May 2018 began in the School of Electronics & Communication Engineering, SMVD University, Katra with an objective to provide an exposure to the faculty members, research scholars and masters’ students in the field of “Emerging Issues in VLSI Design”. Dr. K. R. Jha, HoD (SoECE), welcomed all participants and resource persons, including Dr. Ashwani Rana, NIT Hamirpur, Dr. Samaresh Das, IIT Delhi and Mr. Tarang Agrawal (Senior Verification Engineer) from ARM Embedded Technologies, Bangaluru. The FDP Coordinator, Dr. Vijay K. Sharma, informed about the importance of VLSI design, its applications and various challenges in the modern era of Electronics. Dr. Sachin K. Gupta, FDP Coordinator, reported that the event attracted nationwide participation from various reputed institute and industry, such IITs NITs, and G. B. Pant Engineering College from Uttar Pradesh, Gujarat, Andhra Pradesh, Punjab and Jammu and Kashmir to mention a few.

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